Serial communication systems are widely used for the transfer of information between devices. Typically, serial communications involve the use of a serializer block to convert a parallel data source into a serial stream and the associated use of a deserializer block to return the stream to its original state. Generically, such communication systems are known as “SerDes” interfaces. PCI Express (PCIe) is one example of such a serial interconnect technology, promoted by the PCI-SIG (Special Interest Group). PCI Express technology is a low cost, highly scalable, switched, point-to-point, serial I/O interconnect. PCI Express is a layered architecture including at least a transaction layer, a data link layer and a physical layer. The transaction layer is responsible for transporting read/write requests from software to the I/O devices. The data link layer is primarily responsible for ensuring reliable delivery of packets across the PCI Express link. The physical layer (PHY) handles the low level PCI Express protocol and signaling. The PHY layer consists of a dual simplex channel implemented as a transmit and a receive pair. The combination of a transmit and receive pair are commonly referred to as a lane. The current standard, PCI Express 3.0, uses a 128b/130b encoding scheme and an 8 GT/s bit rate to provide a bandwidth capacity of 1 GB/s per lane.
An ongoing trend in the design of modern communications equipment is the drive to increase the power efficiency of the devices. Particularly with mobile devices or other battery-powered devices, greater power efficiency is almost a universally desirable attribute. To that end, various types of power saving mechanisms are often employed.
At a fundamental level, any communications system may be viewed as including a receiver portion and a transmitter portion. With regard to the receiver portion, one power savings strategy is to operate the receiver in one or more low power modes, or power save states, as frequently as practical and for periods of time as long as practical, as opposed to the full power, active state. Although some degradation in overall throughput or latency may occur, this often may be balanced against the power efficiency gained.
In further regard to a communications system embodied as a serial link between a receiver portion and a transmitter portion, these power savings techniques may include the use of a receiver detection module, such as one implementing electrical idle detection logic, configured to receive an appropriate idle signal from the transmitter portion for coordinating a power save state for the serial link. The receiver detection module typically places the receiver in active state on the basis of a first state of the idle signal and places the receiver in power save state on the basis of a second state of the idle signal.
For mobile high-speed data communications, it is desirable to have a high-speed, low-power interface. While PCI Express is recognized as a preferred high-speed interface, PCI Express is not recognized as a low power solution for mobile devices where battery life is critical. Accordingly, there is a need in the art for a method and apparatus that significantly reduces the power consumption of PCI Express interfaces and other serial communication systems.